As the electronics industry of today is increasingly finding that the design and manufacture of integrated circuit (IC) packaging substrates is being challenged to ever greater degrees by the increased performance demands of advanced highly integrated IC designs, there is need to reconsider design and manufacturing methods used in their construction. One of the areas of challenge is related to control of electrostatic discharge (ESD) in IC packages. ESD is capable of damaging or destroying IC chips. Moreover, the concern is magnified as the feature size on these chips become smaller. Traditionally, ESD protection is provided on the chip. However, this causes the chip design to allocate valuable chip real estate to create the circuits capable of preventing such damage. In addition, the creation of on chip ESD protection reduces the I/O performance of the chip. ESD protection circuits add load capacitance to I/O which, for high speed signals, affects the ability of the I/O signal to switch quickly.
Methods and structures that remove ESD protection from the chip can provide significant benefit by allowing smaller and less expensive chips to be designed while simultaneously providing higher levels of performance. Without protection from ESD, IC circuitry can be fatally damaged by inadvertent discharge of static build up. Worse yet, ESD damage may not manifest itself right away and result in a failure much later in an IC's life. The static charge itself can be generated and discharged in accordance with a number of natural causes and there have been models developed to aid in the determination of how much protection is required in different circumstances and environments.
There are three primary ESD models for determining protection needs for integrated circuits. The first model is the human body model which simulates the ESD event when an individual, being charged to either a positive or negative potential, comes in contact with or touches an IC. The highest protection classification (Class 3B) for this model is greater than 8000 volts. This means that the ESD protection circuits must safely dissipate voltages over several thousand volts. The second model is the charged device model which simulates an ESD event where a device charges to a certain potential and brought into contact with a conductive surface at a different potential. The highest protection classification (Class C7) for the charged device model is greater than 2000 volts. The last model is the machine model, which simulates the ESD event that occurs when a part of an equipment or tool comes into contact with a device at a different potential. The highest protection classification (Class M4) for the machine model is less than 200 volts. Of these models the human body and charged device models are considered to be most relevant to “real world” conditions and concerns.
So as not to stress ESD protection circuits during manufacturing a variety of different techniques are employed. The most fundamental method is to make certain that all elements of the system, including people, are fully grounded to prevent the buildup of charge in the first place. A second method is to ionize the air to neutralize any charging of the air itself. Most important, ESD protection is a necessary element within a semiconductor device itself. Semiconductors commonly have an ESD circuit to protect their input/output signal paths from electrostatic discharge. Typically, the ESD circuit is integrated within the IC as part of the overall circuit design. Protection at the die level is commonly designed to have the circuit protect the IC at human body model levels, which is the most challenging, and consequently most likely to cause problems for high speed I/O (multi-Gigabit rates)
Given the risk to the ICs there is an obvious and ongoing need for the creation of some measure of ESD protection circuits on the chip itself. The most commonly implemented solution is applied near the I/O terminals. Unfortunately there is a price to be paid for putting protection circuit on the chip and it comes in the form of both reduced active silicon yield (because of the space on the chip consumed by the protection circuits) and the reduction in IC performance due to the parasitic capacitance associated with these protective circuits. Even a well designed ESD protection circuit can add several picofarads worth of capacitance thereby rendering the I/O unusable for high speed operation. However, if one could move most of the ESD protection off of the chip and into the package, or split the ESD protection between the chip and package, significant benefits in both cost and performance are possible. There would still be need for machine model levels of ESD protection on the chip but such circuits would be much smaller and more space conservative and less damaging to high performance.
ESD control methodologies for improving performance described in the prior art have placed an IC and separate ESD protection together in a single package to protect and enhance the performance of the integrated circuit die, one of the shortcomings of those methods is that they require the use of off chip semiconductor devices to switch current surges to ground, which increases assembly complexity. Thus ESD remains a recognized peril to integrated circuits. With semiconductor features shrinking, it is becoming increasingly more difficult to protect the delicate internal transistors and still maintain performance and while current solutions are adequate for the moment, the inclusion of human body model ESD protection on the chip will remain both expensive and performance limiting and there is need to find other solutions. Readjusting how and where ESD protection is applied is certain to yield significant benefits to the electronics industry and alternative methods are herein disclosed that provide the necessary ESD protection at a lower cost than current approaches.